Marker Generator Circuit

The marker generator circuit explained here is a constant- frequencyoscillator driving into a CMOS divider chain.

Switchable out- puts from the divider chain are selected to drive a pulse generator.

The oscillator is C1a in which R1 biases the IC into
linear operation. The crystal determines the basic frequency of
operation at 4 MHz in conjunction with C1, 2, 3 and 4 which appear to
the crystal as one parallel capacitor. The capacitor C2 is  used to tune
the oscillator exactly to frequency as explained in the text. The
resistor R2 adds extra phase shift but also reduces the gain. Thus if
the oscillator is slow in starting reducing R2 may help. The output of
the oscillator is buffered from the rest of the circuit by IC1 /b. lC2
is a CMOS dual type D flip flop that divides the 4 MHz by four to
provide an out put of 1 MHz, the 2 MHz also being brought out.  A
further dual division by 10 is provided by lC3 which therefore provides
outputs of 100 kHz and 10 kHz. The required output is selected by SW1
and applied to C5 and R3 which differentiate the square wave output of
the divider. The waveform is then amplified and squared by IC1/c to
provide an output train of narrow pulses, ‘the amplitude of which may be
varied by means of RV1