How to Design IC 555 Astable Circuit


The post explains how to design a IC 555 astable multivibrator circuit through formulas and calculations.

Free-running multivibrator or Astable multivibrator is a circuit that generates rectangular wave. This circuit in comparison to others can run by itself i.e. it does not require any external trigger to run.

However, in order to design the astable circuit the first care that should be taken is to ensure 555 IC is in a working condition.

To develop an astable multivibrator does not involve a complex process as it can be developed by adding a capacitor and resistors into the Timer IC. The capacitor and the resistors connected to the IC helps to determine the output [High or Low]. The diagram in below illustrates the circuit.


design 555 astable circuit


The Pin1 is laid in ground state. Pin 4 and Pin 8 are first shorted and is then connected to generate +Vcc.

The output i.e. VOUT is adapted from Pin 3. Pin 2 and Pin 6, which are also shorted is connected to the ground via Capacitor C.

Pin 7 on the other hand supplies +VCC via RA resistor. RB resistor is connected in between of Pin 6 and Pin 7. Furthermore, the Pin 5, there are two options: applying modulation input or connect F with a bypass capacitor 0.01.


How it operates?


In order to understand the way Timer 555 works as free-running multivibrator, here lies a circuit diagram as given below



Referring to Fig 1.1, when VOUT output is in high state or Q in low state, the transistor in discharged state is disconnected.

The capacitor C then charges towards VCC via RA and RB resistance, thus keeping the charge time C as constant (RA + RB). However, this makes the voltage threshold go up to +2/3 VCC.

The Comparator 1 generating hi-output and also enabling the flip-flop, in order to keep Q high and output low. With Q in high state, there become saturation of discharge transistor and Pin 7 gets grounded so as to enable Capacitor C can discharge via RB resistance keeping the discharged time constant to RBC.

As the capacitor gets discharged the voltage triggered at the inverting input of Comparator 2 gets discharged. As the input goes down to 1/3VCC, the Comparator 2 output increases.

This result reset of the flip-flop in order to keep Q low and output of the timer high and it further proves that the output of auto-transition goes from low to high and vice versa, further continuing the repetition.


Designing a 555 IC astable multivibrator circuit (calculations)


It is vital to note that the charging time of Capacitor C from 1/3VCC to 2/3VCC is equal to the output time when high, which is equated as tc or THIGH = 0.693 (RA + RB). The following section shows the inference:

At any point of the charging period of the capacitor’s voltage is signified as VC= VCC(1– et/RC)

The charging time of the capacitor from 0 – 1/3 VCC is calculated as: 1/3 VCC = VCC (1-e t/RC )

The charging time of the capacitor from 0 – 2/3 VCC is calculated as: t2 = RC loge3 = 1.0986 RC.

Therefore, the time consumed by the capacitor for charging [from +1/3 VCC – +2/3VCC) is:
tc = (t2 – t1) = (10986 – 0.405) RC = 0.693 RC

Further upon substitution of R = (RA + RB) as in the above mentioned equation we get:

THIGH = tc = 0.693 (RA + RB) C [NOTE: RA & RB in ohms, C in farads)

The discharging time of capacitors from +2/3 VCC – +1/3 VCC equates to when the output time is low and is shown as:

td or TLOW = 0.693 RB C [Note: Here, RB in ohms, C in farads]

However, following is the process of the equation:

At any point during discharge state, the voltage maintained across the capacitor is signified as: VC = 2/3 VCC e – td/ RBC OR td = 0.693 RBC

Oscillation period [overall], T = THIGH + TLOW = 0.693 (RA + 2RB) C. The oscillation frequency as the reciprocal of T is signified as: f = 1/T = 1.44/ (RA + 2RB) C

The aforementioned calculation signifies that the oscillation frequency remains independent of + VCC [Supply voltage collector]


NOTE: Duty cycle term is often used together with astable multi-vibrator.

The time ratio tc, duty cycle when output in high state in respect to T [Total time period] is stated as:


% duty cycle, D = tc / T * 100 = (RA + RB) / (RA + 2RB) * 100


Based upon the aforementioned equation it has become evident that the output of the square wave [Duty cycle 50%] cannot be achieved until and unless when RA = 0.

Furthermore, there is also possible issue to short RA resistance to 0. Keeping RA = 0 ohm, terminal 7 has its direct connection to +VCC followed by repetition of the cycle.

When capacitor is discharged from transistor and RB the transistor receives extra current from VCC via a short in between of +VCC and Pin 7. This situation may put risk damaging the timer and the transistor.

If there is a need to acquire symmetrical square wave it can be done if a diode can be connected across RB resistor.  Capacitor C get its charge Diode D and RA to +2/3 VCC (approx.) further discharging via the transistor [Terminal 7] and RB [Resistor] till the voltage of the capacitor goes down to 1/3 VCC and further repetition of cycle. In order to avail output in square wave, RA must be combined of a pot and a fixed resistor R. This will help to acquire the correct square wave.

While 555 is used extensively these days, it is rather better to use 7555 [a CMOS version of 555]. This actually saves from high current input and noise control.